The invention relates generally to semiconductor memories and, more particularly, to noise suppression techniques for use therein.
Dynamic random access memories (DRAM) are the semiconductor storage devices of choice for maximizing the number of data bits stored per unit surface area on a chip. A typical IT DRAM cell includes only a single MOS access transistor and a corresponding storage capacitor. In contrast, a static RAM cell includes between 4 and 6 MOS devices. During DRAM cell operation, the storage capacitor holds one level of charge to represent a xe2x80x9clogic onexe2x80x9d and another level of charge to represent a xe2x80x9clogic zero.xe2x80x9d The access transistor is used to controllably couple the storage capacitor to a bit line during read and/or write operations.
It is often desirable to embed a DRAM storage device within logic circuitry to provide high-density, on-chip storage capabilities for the logic circuitry. In such a system, it is preferable that the DRAM storage device be implemented within the logic with little or no change in the logic process. It is difficult, however, to achieve a good, high capacity DRAM storage capacitor within an embedded DRAM device without changing the logic process. For example, the storage capacity of planar storage cells in embedded DRAMs is usually between 1 and 5 femptofarads (fF) as opposed to conventional cells having capacities between 15 and 20 fF. In addition, because of their physical dimensions, these capacitors have a limited range of voltages that can be impressed upon them. The small capacity and limited voltage range of these structures limits the overall voltage swing that can be developed using these capacitors during DRAM operation. Because of the low voltage swing associated with embedded DRAMs, noise is more of a problem in these devices. The two greatest sources of noise in DRAM devices are (a) bit line to bit line noise coupling and (b) word line to bit line noise coupling. Word line to bit line coupling is especially large in embedded DRAMs because of the greater gate to source overlap coupling in the access transistors of these devices.
As is well known in the art, an open bit line architecture is capable of achieving a significantly greater cell density than the more commonly used folded bit line architecture. For example, use of an open bit line architecture can increase cell density up to 100 percent or more over the folded bit line approach. Therefore, to achieve a maximum cell density, the open bit line approach is preferred. However, the open bit line architecture is more susceptible to bit line to bit line noise due to the closer proximity of the switching bit lines within the structure. As described above, this increased noise can be especially damaging in embedded DRAM devices.
Therefore, there is a need for an open bit line DRAM architecture that is capable of low noise operation. Preferably, the architecture will be capable of implementation within an embedded DRAM structure with little or no change to the logic process.